As the designs become more complex, the amount of time required to verify them increases dramatically. Consequently engineers that can do both design and verification can simplify the task of any project managers.

This is why, on top of verifying his own designs, to ensure first silicon success, Pierre has also been responsible for the verification of other people’s designs. He has developed excellent strengths in the Verification of Integrated Circuits.

His experience includes:

  • Creation of verification plan and testbenches for his own designs.
  • Creation of verification plan and testbenches for various designs for which he was not the designer.
  • Managing and developing¬† the structure (test harness) and functions to verify complex devices.
  • Developing assertions (PSL) to verify designs dynamically (testcases) and statically (formal analysis).
  • Creation of scripts to handle regression testing and to provide a GUI for the verification and for the design engineers.
  • C-code development for System-on-Chip (SoC) verification with embedded processors.

His abilities to write good directed testcases have helped him find and correct many design’s problems before tape out. More recently, Pierre has worked with formal analysis tools to enhance further his abilities to find bugs earlier in the design phase. He can now use assertions successfully to verify complex designs for formal analysis and for dynamic tests.

Pierre has superior abilities in debugging and correcting all sorts of design and verification problems found during the development of a project. He has successfully debugged test cases at all the stages of the process: RTL, gates with zero delay and gates with fully annotated nets. He has also verified complex RTL code (filters) by writing their equivalent in C-code and checked that the two models match perfectly.

Pierre has written harness and test cases in both Verilog and VHDL (although he is more familiar with Verilog).

Pierre’s RTL design expertise provides him with the ability to, not only tracks down bugs quickly but also to suggest proper RTL fixes to the design team.